An embodiment of the present invention relates generally to a semiconductor memory device, a memory system and a method of manufacturing the semiconductor device and, more particularly, to a semiconductor device including pads and gate lines, a memory system and a method of manufacturing the semiconductor device.
With continued miniaturization of highly-integrated semiconductor devices, line width and space width of patterns decrease in order to increase the number of patterns within a limited space. In general, patterns are formed by using a photolithography process. However, decreasing the pattern width and the space width between patterns have limitations due to a resolution limit of the photolithography process.
Therefore, technologies for forming fine patterns beyond the resolution limit of the photolithography process have been proposed, for example double patterning technology for forming fine patterns by double overlapping patterns and spacer patterning technology using spacers to form fine patterns.
Since semiconductor devices require pads and corresponding gate lines, a layout for an efficient arrangement of the pads and the gate lines in a limited space is useful.